The models are first simulated and the results are compared and then the experimental results are presented.
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In voltage mode control an external signal is compared with the control signal obtained for generating the duty cycle needed to have the wanted output voltage. The output voltage Vout is monitored and subtracted from the reference value Vref and an error signal Vcomp results. This error signal is then used for the resulting control signal. The control signal is then compared with the external ramp voltage Vramp and a pulse width modulated signal is sent to the drivers of the MOSFET so that converter can react in such a way so as to reduce the output error , , , .
Figure 3. For simplification, we can combine the transfer function of the PWM modulator and the buck converter power stage as: ………………………………… The roots of the polynomial in the denominator of 3. Similarly the roots of the numerator of 3. The transfer function of the power stage is a second order system with a double pole at the resonance frequency of the LC filter and a zero produced by the ESR of the capacitor.
Line to output transfer function is given as: ……… Output impedance is given as Closed loop output impedance is given as One pole is located at the origin to realize high DC gain and the relevant components values are given as: Loop gain crossover frequency: ………………………………………………… ….. It is the zero crossover frequency defined as frequency when loop gain is unity.
Since ………………………………….. The poles and zeros of the compensator will be placed as follows: ……………………………………………….. The other zero of the compensator is chosen using the following formula: ………………………………………….. The control signal is compared to a repetitive reference waveform at the desired frequency. The switch control signal changes according to the output of the comparison.
The switch signal can be viewed as a pulse train with two states: on and off. The Pulse Width Modulation is the method where the width of the on-part and off-part of the switch signal are modulated to get the desired behaviour. In other words, the method decides for how long the switch will be turned on .
The pulse-width generator equivalent generates the pulse-width modulation to control the N-channel MOSFET to either switch it on or off. The components value of the power stage is selected to be the same with the selected values in Table 2. Load is selected to be 1 ohm and the input voltage is set to 12 The current probe and voltage probe is used to measure the voltage and current at the inductor and the load respectively.
From the waveform shown in the figure 4. The output voltage equals 4. The output power is The related waveforms obtained from the simulation are shown as below. Figure 4. The pin out above shows the commonly used interfaces and their locations. Note that all the numbered pins p5-p30 can also be used as digital in and digital out interfaces. The mbed Microcontrollers provide experienced embedded developers a powerful and productive platform for building proof-of-concepts.
For developers new to bit microcontrollers, mbed provides an accessible prototyping solution to get projects Prototyping form-factor I. Lightweight Online Compiler II. Cookbook of published libraries and projects 4. Combined with the wealth of libraries and code examples being published by the mbed community, the platform provides a productive environment for getting things done. Powered by USB or 4.
Real-time clock battery backup input VB IV. Requires 27uA, can be supplied by a coin cell VI. Current limited to mA IX. Digital IO pins are 3. Pull up resistor is on the board, so it can be driven with an open collector V. A digital pin can drive 40mA, up to a total of mA. The board is connected to the host computer using USB cable. It provides power to the MCB The board itself is relatively simple, and aside from the LPC itself there are only a few support circuits mostly RS level converters, Ethernet transceivers, audio amplifiers and so on.
It also provides a full- colour LCD display. A phase-locked loop or phase lock loop PLL is a control system that generates an output signal whose phase is related to the phase of an input "reference" signal. It is an electronic circuit consisting of a variable frequency oscillator and a phase detector. The signal from the phase detector is used to control the oscillator in a feedback loop.
There is a block of KB of flash memory, located at the bottom of the address space, which is used for storing your code and data. All the peripherals are memory-mapped, so they are accessible directly from C. The board can withstand a maximum voltage of 3. The most difficult part is determining the compensation network and manipulating the poles and zeros to build a robust and balanced system. The PWM is a relatively simple concept, but a real world design of this block would be troublesome. Design and simulation of the circuit is done using Orcade PSpice.
PID controller has been designed and the system operates in closed loop. In other words, feedback stabilizes the system. Phase margin and gain margin has been obtained and stability analysis of the closed loop system has been studied using MATLAB. Improvement in the transient response of the converters through the use of a feedback path with proper compensation has been achieved. There are many types of configuration for buck converter control available in the market.
For instance, there are synchronous buck converter, peak-current control buck converter and etc. Thus, this project could be expanded by implementing peak-current mode control or synchronous buck configuration into the voltage-mode control buck converter for improvement in the controlling of the output voltage. By improving the control method for the buck converter, the complexity of the design will arise, thus it will need more research to be done in the future for such improvement. Finally, even after such improvement, there will be more research that could be done to improve the efficiency and reliability of the converter.
Rahimi, Parviz Parto, and PeymanAsadi. Kalirasu and S. In order to facilitate the soft switching transitions, independently programmable delays between the two output waveforms are provided on these drivers. The de- lay pins also have true zero voltage sensing capability which allows imme- diate activation of the corresponding switch when zero voltage is applied. In the UC series, the two outputs are configured in a true complementary fashion. Note 2: Consult Packaging Section of databook for thermal limi- tations and specifications of packages.
AUX is capable of sourcing 0.
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During sleep mode, AUX is inactive with a high impedance. The ENBL input will place the device into sleep mode when it is a logical low. GND: This is the reference pin for all input voltages and the return point for all device currents. It carries the full peak sinking current from the outputs. Any tendency for the outputs to ring below GND voltage must be damped or clamped such that GND remains the most negative potential.
It should be noted that if the input signal comes from a controller with FET drive capability, this signal provides another option. This output is capable of sourcing 1A and sinking 2A of peak gate drive current. T1, T2: The resistor on each of these pins sets the charging current on internal timing capacitors to provide independent time control. The nominal voltage level at each pin is 3V and the current is internally limited to 1mA. The total delay from INPUT to each output includes a propagation delay in addition to the programmable timer but since the propagation delays are approximately equal, the relative time delay between the two outputs can be assumed to be solely a function of the pro- grammed delays.
The relationship of the time delay vs. RT is shown in the Typical Characteristics curves. Either or both pins can alternatively be used for voltage sensing in lieu of delay programming. This is done by pulling the timer pins below their nominal voltage level which immediately activates the timer output. This pin should be bypassed with a capacitor to GND consistent with peak load current demands. RT Typical application with timed delays. Using the timer input for zero-voltage sensing. Synchronous rectifier application with a charge pump to drive the high-side n-channel buck switch. UDG Figure 4.
Self-actuated sleep mode with the absence of an input PWM signal. UDG Using an N-channel active reset switch with a floating drive command. UDG Figure 6. Typical forward converter topology with active reset provided by the UC driving an N-channel switch Q1 and a P-channel auxilliary switch Q2. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design.
Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used.
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TI is not responsible or liable for any such statements. This datasheet has been download from: www. B IRF 9. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA NOTE: 1. Repetitive rating: pulse width limited by Max junction temperature.
See Transient Thermal Impedance curve Figure 3. As used herein: 1. Life support devices or systems are devices or systems which, a are intended for surgical implant into the body, or b support or sustain life, or c whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Ridley, F. Spangler, A. Tang, F. Lee, R. Ridley, I. Tang, Y. Hua, F. Lee, I. Endo, T. Yamashita, T. Maksimovic, R. Power Electron, Conf.
Mwinyiwiwa, P. Mwinyiwiwa, X. Wang, G. Oruganti and M. Takahashi, R. Madigan, R. Ericson, E. Conference, pp. Elmore, W. Peterson, S. Record, pp. Umanand and S. Zhang, L. Yang and C. The advantages of a high power factor and low harmonic distortion are well known. A major advantage is an optimum utilization of power coming out of the utility [1, 16—18]. The past two decades have witnessed a tremendous research effort related to power factor correction in switching power supplies [1—49].
This could be attributed to the growing awareness about power quality and the seriousness with which the concerned agencies all over the world have started enforcing power quality standards. For purposes of highlighting the novelty of the present invention, prior art schemes will be reviewed first.
The major issues [2—4] concerning power factor correction circuits are the size and the cost of the system, complexity of the circuit topology e. In earlier days, the trend was to use a boost topology and to modulate its duty cycle, so as to present a resistive load to the line voltage. But any such scheme needs a second stage for isolation and load voltage control. A simple scheme based on a flyback converter operating in a discontinuous current mode DCM with constant duty cycle is reported by Erickson et al , with isolation incorporated in the first stage.
A new power factor correction scheme for a single-phase buck-boost converter is proposed by Prasad et al . Some of the single stage configurations proposed are the isolated boost topology proposed by Yang et al , a fast-response topology utilizing the inherent characteristics of resonant boost stage by Kheraluwala et al  and the dual switch forward topology proposed by Daniele et al . But these approaches all utilize at least two switches. Redl et al  proposed a new family of power factor corrector circuits S 2 IP 2 , which overcame most of the drawbacks of then-existing configurations.
Merged configurations of derived boost and buck configurations have also been used for power factor correction PFC [10,11]. Other authors reported on related aspects including reduction of high-voltage stress on primary side devices  and electromagnetic interference EMI in PFC circuits [13,14].
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After this initial overview, the underlying ideas and classification of the various PFC techniques are presented next. More literature review is taken up subsequently. In addition to the above, the following may also be desirable depending on the specific application:. For example, a supply with sufficient hold-up time can keep providing power to the load during short power outages. Hence, these solutions are simple, reliable and cost-effective at low power levels.
But they suffer from the following disadvantages:. They do not attempt to improve it beyond what is required by the standards. Thus they still do not facilitate an effective V-A utilization. Because PPFC uses only passive components therefore cannot maintain output regulation when the input fluctuates over a wide range. To accommodate a wide range of voltage variation one must use active switches and duty cycle control. For a duty cycle controlled system, for example, a duty cycle ratio range of 0. To allow a wider variation, this range could be widened to 0.
However, this will require very high t r and t f times of the switching devices. Therefore, these are expensive techniques as compared to PPFCs. Nevertheless, their overall performance is far superior. The boost and flyback topologies are operated in continuous current mode CCM or discontinuous current mode DCM [7, 27, 33]. It should be noted that:. The major disadvantage is high peak currents. Thus, DCM operation commends itself by permitting the use of smaller transformers.
But it has the disadvantage of higher peak currents. In APFCs, the input line current is controlled by various techniques such as peak current mode control, average current mode control [12, 26], charge control [17, 18, 32, 33], hysteresis current mode control [15, 16, 30, 31], sinusoidal pulse width modulation PWM [14, 28], delta modulation control [21, 22, 36, 37], inductor voltage control [23, 40], etc. In fact, many of these control schemes are available as ICs. APFC could be both current source type usually buck type [36, 37] or voltage source type [1, 2, 26].
The voltage source type, which is more popular, may use buck, boost, buck-boost, cuk or derived topology. The following points must be noted regarding these configurations:. But this configuration suffers from the demerits of high reverse recovery loss, charge pumping loss, poor EMI performance and to some extent even cusp distortion near the zero crossings of the input current. Some of these problems may be alleviated using soft-switching techniques and resonant power conversion techniques.
Also, the peak current stresses on the devices are greater. It offers several advantages. For example, the start-up in-rush current problem is not present, overload protection may be easily implemented, the output voltage may be greater or less than the peak input voltage and galvanic isolation is possible. The diode reverse recovery problem is eliminated when operating this topology in the DCM mode. A higher rated capacitor will result in increased cost and greater power loss due to larger ESR values.
Some of the drawbacks mentioned above e. The first stage corrects the power factor while the second stage provides tight regulation of output voltage against fast, dynamic load. The disadvantage with this scheme is lower efficiency because of two stages. This disadvantage is overcome to some extent by merging the two stages of a cascade configuration into one power stage [44, 45]. This increases the efficiency but the control becomes complex. Many power factor corrected circuits belong to this category. An example of this scheme is where the active power factor correction circuit operates only during some portion of the input AC waveform, while in the remaining portion, a passive network PPFC , connected in parallel with the APFC circuit, takes over.
The present invention employs a single-stage, single-switch, input-output isolated converter configuration using a hybrid combination of forward and flyback converter topology. It uses a novel control scheme based on duty cycle control in conjunction with two discrete operating frequencies. A continuously varying operating frequency is not required, reducing the complexity of the control circuit.
It results in reduced peak current stress on the circuit components leading to higher circuit reliability. Since the converter operation switches between two operating frequencies, its noise spectrum spreads out  making it more electromagnetic compatible EMC. The cost is substantially lower than prior art multiple-stage and multiple-switch APFC designs and operates with high power factor and a well-regulated DC output voltage.
One particular embodiment of the invention is in the form of a fully self-contained power converter module. The proposed configuration can be further integrated to reduce system size and will be of especial interest to industries associated with battery charging and uninterruptible power supply UPS systems. L and C are the filter elements for THD reduction. The output rectifier diodes are connected in a special, novel configuration. For illustration, these points are marked on one of four change over points within an AC cycle.
As is clear from the brief review presented in the preceding sections, the existing schemes suffer from one or more of the following drawbacks:. Further, buck applications requiring 12V, 24V and 48V supplies are generally not possible. Both Single Stage and Multiple stage converters employing one or more switches have been extensively used as power factor correction stages in all sorts of systems. The present invention is based on the following objectives:.
This configuration is proposed to reduce the size of the transformer, as a major advantage. When this circuit is operated in conjunction with the proposed control scheme, peak currents are substantially reduced. It should be noted that the output rectifier diodes in FIG. It is novel because the secondary rectifiers are not connected in the manner of a traditional bridge rectifier.
It is connected to facilitate the combination of flyback and forward mode of operation. According to the proposed control strategy depicted in FIG. The point where phase 1 changes to phase 2, is called the phase change over point PCOP. During phase 2, the duty cycle is continuously modulated in a sine-weighted manner. At some suitable point beyond PCOP, the switching frequency is changed from f 1 to f 2. It should be noted that only two discrete values of operating frequency are used. A continuous frequency control which is more complex is not used here. The output voltage regulation is achieved by using a PWM technique.
As the load increases, the duty cycle increases and vice versa, to maintain the output voltage constant. The instant at which the frequency is doubled FCOP is selected to achieve good power factor.
The power stage and the control stage have been integrated into a single compact, module. This results in higher reliability. The details of the design and fabrication of this module are presented in later sections. To summarize, the present invention provides a novel scheme based on duty cycle control in conjunction with two discrete switching frequencies. The scheme is depicted in FIGS. It should be noted that a continuous, variable frequency control is not employed here—rather, the system is made to operate with two different switching frequencies.
This control scheme is an improvement over an earlier work , which used a single, constant frequency and two fixed duty cycles, depending on the comparison of the rectified input voltage and the reflected output voltage. For example, this configuration will be of interest to industries associated with battery charging and UPS design and fabrication work.
An added advantage of this scheme is the reduction of EMI of the system due to bi-frequency modulation . Since the converter operation switches back and forth between two operating frequencies f 1 and f 2 , the frequency spectrum will spread out showing more frequency components, but with smaller amplitudes.
In comparison, if the converter is operated only at one fixed operating frequency, its spectrum will be narrow but the amplitudes will be higher, increasing the EMI magnitude and reducing the systems electromagnetic compatibility EMC. In view of the anticipated wide application of the proposed configuration, attempts have been made to realize a smart module which integrates the power stage with the control stage. This makes the system compact and enhances the reliability and efficiency of the system as compared to the corresponding discrete system.
Hence V i , is a full wave rectified sine waveform. It should be obvious to those skilled in the art that the functions provided by diodes D 5 —D 8 can suitably be accomplished through the use of lower loss Schottky barrier diodes or synchronous rectifiers such as low loss MOSFETs. To achieve the required output voltage, the transformer can be excited in three different modes. Here X 1 is used as a pure transformer having a large magnetizing inductance. Hence, the secondary voltage, V s is given by:. Those of skill in the art will appreciate that D 5 and D 6 conduct current to charge the capacitor C o through inductor L.
When switch M is off, diodes D 7 and D 8 conduct current to release the magnetizing energy into capacitor C o. If the magnetic flux does not reach zero in these designs, the size of the core and hence of the transformer will need to be increased to accommodate the energy transfer. Further, if uniform duty cycle is maintained throughout the cycle, then I in will be sine-weighted. Hence, the switch has to handle a maximum current of four times the peak input sine current in the case of a discontinuous mode for I L. Similarly, diodes D 5 and D 6 must handle four times the peak current of I in.
It is preferable to operate the system in a discontinuous mode for realizing zero current turn-ON for switch M and to reduce the size of inductor L. In this mode diodes D 5 , D 6 and inductor L are not necessary and diode D 8 is forward biased. Further, transformer X 1 has a finite inductance in the N 1 winding so that the required energy can be transferred to the load. Under these conditions, when the switch is ON, primary current I M ramps up from zero current zero-magnetizing flux , at the beginning of the cycle. When the switch is OFF, diode D 7 conducts current to transfer the energy to the load.
Again, if the duty cycle is uniform throughout the cycle, then input current I in becomes sine-weighted. In the earlier two cases, the transformer, diodes and switches have to be rated for a higher RMS current rating because of the high peak current requirement. By operating the system in a mixed mode, the root mean squared RMS current rating of the diodes and the transformer, X 1 , can be reduced. If we assume that half the energy requirement during this period is supplied by voltage mode and the other half by the flyback mode, then the peak current will become half for the diodes and the transformer resulting in a reduction of RMS rating of these devices.
Let L 1 be the primary inductance of transformer X 1 and T 1 be the period of the switching frequency. From 7 , the required current is obtained as:. If Eqns. Under this condition the peak current requirement of the secondary and D 5 —D 8 are reduced to half the value as compared to the voltage or current mode. During this interval, Eqn. The point where the first phase changes over to the second phase is called the phase changeover point PCOP as mentioned before.
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During the first phase of operation, the switching frequency is the first fixed frequency f 1 and during the second phase of operation, the switching frequency is the second fixed frequency f 2 and the changeover from the first frequency to the second frequency can be anywhere above the phase changeover point to realize good input current waveforms. FCOP may be selected using computer simulation. For completeness of the disclosure, and for comparison purposes between the design and the implementation in accordance with the invention, the line voltage, line current and the output voltage in accordance with the described simulation are shown in FIG.
The line current and voltage show a slight phase difference because a filter was used to clean up the current waveform of high-frequency components. Hardware Implementation and the Smart Power Module. The combination mode discussed in the previous section and simulated using PSPICE, has been implemented and tested using a laboratory prototype of the designed rating. The block diagram showing the control stage is shown in FIG. The components in FIGS. In FIG.
Cheap buck converter design deals
The expression for T ON can also be written as:. From FIG. Otherwise, M 1 and M 4 are ON and control phase 2 is in operation. V R has a waveform determined by the data stored in Table 1. This controls I R accordingly and hence the pulse width through V E at pin 5. The value of k is fixed which is set by the user at the beginning of his experiment or application. The value of kV o varies as V o varies with load. Rather, it represents a sine-weighted string of duty cycles that the MOSFET should operate with at various time instances of the input AC waveform, so that a sinusoidal current is drawn from the input AC supply.
This can be further understood with reference to FIGS. The overall control strategy may be described as follows: The output voltage, V o , is compared with a reference voltage and the error is fed into a proportional controller. During phase 1, the control signal from the proportional controller varies the duty cycle of the monostable multivibrator feeding the gate trigger circuit of the MOSFET so as to maintain a constant output voltage under varying loads.
If the load is not varying, a fixed duty cycle corresponding to the given load is maintained. For lesser loads, the duty cycle will be less as decided by the output of the proportional controller and accordingly the duty cycle at other instants of the AC waveform are automatically scaled so as to preserve their sine-weighted nature. This smart power module integrates the input diode bridge rectifier, the power switch and the high frequency output rectifier bridge with associated drivers and control functions.
The ASPM solution brings a high level of integration, allows minimum number of external connections to offer minimum size and weight solution. Very short internal connections minimize parasitic resistance and inductance. This permits high-frequency operation with reduced voltage overshoots facilitating EMI and RFI filtering and improving overall efficiency. The components dissipating more than 1W are mounted onto a power substrate.
The power stage in FIG. It is clear to those skilled in the art that various component arrangements are possible, so long as the heat dissipation is balanced. This should be viewed with reference to FIG. The substrate simultaneously presents a VRMS isolation barrier to the heat-sink and provides optimum conduction of internally generated heat from losses in the components to the outside world. Lowest cost is achieved at 2. This type of substrate consists of three layers of different materials bonded together, a metal base plate of aluminum, steel or copper with thickness varying from 0.
Power semiconductors, in chip form, are then directly soldered onto the etched copper circuit patterns on the IMS for best heat conduction. Topside connections are made with aluminum wires, bonded between the chips and the copper patterns to complete the circuit. Multiple wires are featured, so as to distribute current uniformly from the top surface of each chip, through the depth of the semiconductor material, then to the backside IMS heat spreader.
Extensive usage of SMD devices helps to conserve space. This control board is fastened physically at a level above the power stage as shown in the cross-sectional view of the power module in FIG. In power applications, reliability considerations dictate that the preferred practice is to employ a small number of large chips, rather than a large number of small chips, in parallel. It also makes eminent sense to incorporate the shunt resistor indicated in FIGS. This shunt device available with backside metallization is soldered to the power substrate and four-wire connections are made with aluminum wire bonding, similar to the power dies.
This arrangement provides excellent power management and optimum voltage feedback. Operating temperature is a key parameter for gauging the expected mean time between failure MTBF of electronic equipments and this is especially critical for power semiconductors. Although careful engineering design will ensure that device temperatures under normal operating conditions are comfortably below danger levels, an accidental rise in either ambient or heat sink temperature could precipitate rapid destruction of the system.
All components dissipating less than 1 W are mounted onto a printed circuit board PCB , which itself is housed in the module body. This PCB incorporates driver, protection and control functions, implemented in SMD technology, as well as components dedicated to the galvanic isolation interface. The various building blocks are as follows:. Silicon chips and other power components 2 , soldered to the top surface of the substrate with electrical connections made via ultrasonically bonded aluminum wires.
Small signal connectors 8. These connectors are available to the user for control circuit inputs e. The choice of components, the layout and method of assembling the smart module serves to illustrate the principles of the invention. It will be obvious to one skill in the art to change the components from the above list to effect desirable results without deviating from principles of the invention. The base plate can have different shapes and sizes, different monitoring, protection, and control functions can be incorporated in the control PCB, different sized connectors or components, etc.
For easy access, connecting posts are placed at the periphery of the module block. The assembly of a complete converter is greatly facilitated by using power module building blocks. An external board with transformer, inductor, filter capacitors and other auxiliary power supply functions completes the package. Labor costs are kept low by extending the building block concept to all elements. The external board is attached to the module with solderable power terminals. Small signal liaisons are by means of feed-through connectors. No wire links are needed, so transient generating parasitics are controlled, from the control board to the power module.
As a direct consequence of this rigorous approach to construction and final assembly, converter performance is both predictably high and uniform. Reproducibility is excellent over very long production runs. A laboratory prototype was fabricated to test the proposed configuration and the control scheme discussed in the previous sections.
It was tested at a power level of up to W. The wattage of the prototype at W is due to the availability of piece parts at the time and the time constraint under which to produce a working model to demonstrate the principles of the invention and not a real limitation of the invention itself.
As can be seen, the line current has negligible harmonic distortion. Those of skill in the art will appreciate how well the invention in its actual preferred embodiment performs in accordance with the PSPICE design simulation although the simulation is for 1 kW, the waveforms nonetheless behave essentially the same , results of which are shown in FIG. A state-of-the-art smart power module has been developed based on a new power converter configuration.
The proposed single stage, single switch converter employs a simple control scheme to provide a regulated DC output voltage and operates at high input power factor. As per FIGS. When the rectified input voltage becomes larger than the reflected output voltage as in phase2 , and the operating frequency is changed to another constant value f 2 at a suitable point FCOP. This provides a significant improvement in the harmonic distortion of the line current. Further, the peak current stress on the devices is reduced with the proposed dual frequency scheme.
All the details of the design and fabrication of the smart power module have been presented. The module is specifically suitable for low DC voltage buck applications. Those of skill in the art will appreciate that other suitable circuit topologies in keeping with the teachings herein are contemplated as being within the spirit and scope of the invention.
Those of skill also will appreciate that certain circuit and material details are illustrative and may be changed without departing from the spirit and scope of the invention.
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Thus the following further detailed discussion of certain design particulars is intended to elucidate one embodiment of the invention and not to represent a limitation placed on the broad scope of the invention. The Area Product A p expression for a flyback converter, operating in complete energy transfer mode, has been used in the design as it is considered to adequately represent the hybrid topology proposed in the invention. The relation is given by:. The following expression is used for determining the transformer's primary number of turns:.
If the primary current is I p and secondary current is I S , then the last equation may be re-written as:. Further, it is preferred that a suitable air-gap be inserted to realize an inductance of 0. It is also preferred that litz or multi-strand wire of suitable gauge depending on the current rating provided be used for windings. It is also preferred to use any appropriate wire gauge to carry 9 A current. Finally, it is preferred that litz or multi-strand wire be used for winding the inductor.
A sample EPROM coding is indicated by Table 1 below for each of four quadrants with hexadecimal H data in sequential hexadecimal addresses, as will be described. If there is a sag and if the control part is able to respond to this, then in the input current waveform also there will be a proportionate sag. Load conditions are taken care of by the controller. Rather, it represents a sine-weighted string of duty cycles that the MOSFET should operate with at various time instants of the input AC waveform, so that a sinusoidal current is drawn from the input AC supply.
The locations still remaining un-programmed, are programmed with C4H. The overall operation will not get affected. But the modulation frequency should preferably be increased to reduce the filter voltage drop and the EPROM data should be suitably changed. For the circuit designed to demonstrate the invention shown in FIGS. Frequency changeover for. The process repeats itself for the subsequent half cycles.
As has been mentioned earlier, the peak currents in the secondary side can be reduced if the current contributed by the flyback action equals that of the forward action. If there is only flyback action, the peak current is given from Eqn. It does not require a continuous variation of operating frequency. The disadvantage namely high peak currents when operating in discontinuous current mode is reduced to a great extent by using the proposed dual frequency control technique.
It is recommended to use Schottky diodes in such a situation. The proposed control scheme works equally well and causes no disadvantages in such an application. With the advancement in technology, low voltage drop and low gate charge devices are now available, which might give them an edge over Schottky diodes for extremely low output voltage typ.